Zen 3 architecture overhaul: double three-level cache capacity, 15% increase in IPC

According tomedia AdoredTV, AMD’s next-generation Zen 3 architecture, code-named Milan, will be improved at the core level, with the goal of improving the IPC performance of the Zen 3 architecture by another 10 to 15% compared to the current Zen 2.

Zen 3 architecture overhaul: double three-level cache capacity, 15% increase in IPC

The Zen3 architecture will still use the Chiplets design that CPU Die separates from I/O Die, but the biggest difference is that a single CCX will have eight cores, while the current Ryzen processor will have four cores and two CCXs to form a CCD.

Perhaps many students can not understand such changes can bring about some improvements!

Previously, although a single CCD is 8 core 32M L3 cache, but divided into 2 CCX, a single CCX is 4 core 16MB cache, the different CCX between L3 cache can not be shared, that is, each core can only call a maximum of 16MB L3 cache. If an application can only support four or fewer cores, the other CCX’s 16MB L3 cache may be idle.

The Zen 3 architecture expands the individual CCX to 8 cores with a built-in 32MB L3 cache, which means that in any case any one core can invoke the entire 32M L3 cache, and the new Zen 3 architecture no longer wastes any L3 cache. Therefore, in some applications that require high single-core performance, this design will greatly enhance the computational efficiency of the processor.

One of the secrets of the 18% increase in Zen2 Architecture IPC is to double the L3 cache capacity, and the Zen 3 architecture is to double the cache capacity that each core can take advantage of again. It’s also that the Zen 3’s L3 cache design doesn’t require additional transistors, which can result in additional IPC performance improvements even without the same process.

PS: The small editor is now very happy with the improvement of the Zen 3 architecture, the previous Zen 1/2 design can not fully utilize the L3 cache, this deficiency in the Zen 3 era will no longer exist!

In addition, the next generation of Zen 4 architecture also has some news!

The Zen 4-framed Ryzen 5000 Series processor will use a new CPU pin design, which means that the existing motherboard iron is not compatible (the Zen 3-framery Ryzen 4000 Series processor is still likely to use the AM4 socket). It will be 5nm in the process and will be extended to the complete AVX 512 in the instruction set.

In addition, the Zen 4 architecture will double the L2 cache capacity, i.e. a single core will be equipped with a 1MB L2 cache.