AMD announced earlier this year that the 7nm-plus-process, Zen3-architecture Ryzen 4000 processor would be released this year, with the latest news coming from the Taipei Computer Show in September. 7nm Zen2 architecture of the Rylong 3000 series desktop CPU release has been 9 months, the current performance is still very powerful, the sales of major e-commerce platforms are still increasing, but AMD’s previous commitment is to release a new generation of products every year, this year will still be the desktop version of the Rylong 4000 series debut.
The Ryzen 4000 series of desktop code nameVermer (Delft painter in the Netherlands), using the Zen3 architecture, the process upgrade to 7nm, that is, the enhanced version of 7nm, but no EUV lithography process, should be concerned about the cost of the EUV process.
As for the release time, it was previously reported that the Ryzen 4000 series will be released at the Taipei Computer Show in May, but the latter has been postponed until September, so AMD also plans to officially launch the Ryelong 4000 series of desktop CPU in September.
As for the Zen3 architecture, the latest news is that the Zen 3 architecture will make some core-level improvements, with the goal of improving the IPC performance of the Zen 3 architecture by another 10 to 15% compared to the current Zen 2.
Specifically, the single CCX in the Zen3 architecture has been expanded from 4 cores to 8 cores, with a built-in 32MB L3 cache, which means that in any case any one core can invoke the entire 32M L3 cache, and the new Zen3 architecture no longer wastes the L3 cache. Therefore, in some applications that require high single-core performance, this design will greatly enhance the computational efficiency of the processor.
One of the secrets of the 18% increase in Zen2 Architecture IPC is to double the L3 cache capacity, and the Zen 3 architecture is to double the cache capacity that each core can take advantage of again. It’s also that the Zen 3’s L3 cache design doesn’t require additional transistors, which can result in additional IPC performance improvements even without the same process.