For the first time, semiconductor carbon nanotubes surpass silicon-based CMOS devices and circuits of similar sizes in real electronicperformance. On May 22nd, Zhang Zhiyong-Peng, key laboratory of the Ministry of Physics and Chemistry of the Ministry of NanodeviceS, published a paper entitled “High Performance Electronics based on high-density semiconductor array carbon nanotubes” (Aligned, high-density semi-semi-carbon nanoarrays) in the Science, the world’s leading academic journal. high-performance electronics).
The paper describes the preparation of high-density high-purity semiconductor array carbon nanotube material on a 4-inch substrate, which breaks through the key material bottleneck of carbon nanotube integrated circuits. Zhang Zhiyong told Yan News that the research team has been able to prepare the carbon tube on an 8-inch wafer, and has developed a fully automatic purification and assembly equipment, fully equipped with mass production technology accumulation.
Requirements for carbon tube materials in large-scale integrated circuits
New materials combat the “short ditch effect”
A transistor the size of a cell is the foundation “brick” that builds a chip. At present, the most mainstream logic circuit designed by the electronics industry is the complementary metal oxide semiconductor (CMOS) technology, made from p-type and N-type MOS transistors. Among them, it is very important to connect the source area and the leak area, a thin layer of semiconductor called the “channel”.
According to the famous description of Moore’s Law, when the price remains the same, the number of components that can be accommodated on an integrated circuit doubles approximately every 18-24 months and doubles its performance. Once the CMOS transistor is reduced to sub-10nm technology node, the length of the channel is shortened, and the “short channel effect” will appear, which will lose some of the device function.
As a result, scientists are exploring new structures or new materials to solve this problem, further improving the energy efficiency of the device.
Among the many new semiconductor materials, semiconductor carbon nanotubes have attracted some attention: it has high electron and cavity migration rates, atomic-scale thickness, and stable structure, making it an ideal trench material for building high-performance CMOS devices.
Zhang Zhiyong-Peng practice spear task force in 2017 in the “Science” published a paper shows that, according to the results of previous experiments, carbon nanotube CMOS transistors can be reduced to 5nm gate length using flat structure, and compared to the same grid length of silicon-based CMOS devices have 10 times the overall advantage of the original performance power consumption.
However, to realize this experimental potential, the technical basis for the preparation, purification and arrangement of materials is also required.
Preparation, purification and arrangement
Carbon nanotubes are multi-layered circular tubes consisting of hexagonal carbon atoms. For a long time, the development of carbon nanotube integrated circuit has been restricted by material problems, the key is to achieve ultra-high semiconductor purity, alignment, high density, large area uniform.
The so-called ultra-high semiconductor purity, high density, the specific indicator is semiconductor purity of more than 99.9999%, density of 100-200 per micron.
Although academics have developed a variety of methods for preparing, purifying, and arranging carbon nanotubes over the past 20 years, this goal has never been neared. This makes the actual performance of carbon nanotube transistors and circuits far below theoretical expectations, and even lags behind at least one magnitude of silicon-based technology at the same technology node.
For preparation and purification, Zhang Zhiyong-Peng Practice Spear Team used multiple polymer dispersion and purification (Multiple-Dispersion Sorting Process) technology to obtain ultra-high purity carbon nanotube solution in the paper.
Preparation and characterization of high-density, high-purity semiconductor carbon nanotube arrays
Then, in terms of arrangement, the research team proposed that the combination of dimension-limiting self-arrangement (Dimension-Limited Self-Alignment) was combined to produce a carbon nanotube array with a density of 120 microns on a 4-inch wafer, a semiconductor purity of 99.99995 percent, and a diameter distribution of 1.45 to 0.23nm, theoretically meeting the need for ultra-large-scale carbon nanotube integrated circuits.
Based on this material, the team prepared field-effect transistors and ring oscillator circuits in bulk, and the carbon-based transistors of 100 nanometers of gate length had cross-conductive and saturated currents of 0.9mS/m and 1.3mA/m, respectively, with sub-threshold swings at room temperature being 90mV/dec; a fifth-order ring oscillator circuit with a yield of more than 50% and a maximum oscillation frequency of 8.06GHz, far exceeds published nanomaterial-based circuits and, for the first time, surpasses a similar size of silicon-based CMOS devices and circuits.
High-performance carbon nanotube transistors
Carbon-based integrated circuits are just getting started
At the end of the paper, it is expected that the future will need to be applied on larger sizes, such as 8-inch wafers, and further purification.
Zhang Zhiyong told The News that the current task force has actually achieved the preparation on the 8-inch wafer. This is a technology that can be mass-produced and is growing rapidly.
In terms of purity, the semiconductor purity of carbon nanotubes currently stands at 99.9999%, but for very large-scale integrated circuit applications, an additional 2-3 orders of magnitude are needed. “Further purification increases process steps, reduces yield, and challenges exist to characterize such high purity that engineering approaches are needed to overcome these challenges.” He said.
High-performance carbon nanotube transistors
Zhang Zhiyong believes that the results of the first experiment shows the performance advantages of carbon nanotube devices and integrated circuits relative to traditional technology, in order to promote the practical development of carbon-based integrated circuits out of the first step.
He said carbon-based chips could complement silicon-based chips when processing technology was not too mature, enhancing the functionality or performance of silicon-based chips, or for use in special occasions. Once the technology matures, carbon-based chips have the potential to develop complete applications and play an important role in mainstream computing.
The first authors of the paper are Liu Lijun, a doctoral student in the Department of Electronics at Peking University, and Han Jie, an engineer, Zhang Zhiyong and Peng Jingyi, co-author of the paper, and researchers from Xiangtan University’s Hunan Institute of Advanced Sensing and Information Technology Innovation, Zhejiang University, and the Naguang Electronic Frontier Science Center of Peking University.
The research was funded by the key projects of “nanotechnology” of the national key research and development plan, the Beijing Municipal Science and Technology Commission, and the National Natural Science Foundation of China.