When it comes to high-performance processors, the x86 is not big enough in front of IBM’s Power, which is not strong enough, IBM has thoroughly opened up the Power Instruction Set, and recently launched Power ISA 3.1, which is expected to be announced in August.
When it comes to IBM’s Power Instruction Set, it’s also a long-standing CPU instruction set, Apple’s early computers used the Power architecture, and now IBM’s mainframes use their own Power processors, the latest generation is power 9, which can have up to 24 core 96 threads (Power supports single-core four-thread technology) with a maximum frequency of 3.3GHz.
Currently top500 supercomputing ranked first and second in the use of Power9 processor and NVIDIA acceleration card, so in terms of high performance Power processor is still very powerful.
At the ISSCC 2020 conference earlier this year, IBM announced the latest version of the Power 9 processor details with a core area of 696mm2 (approximately 3-4 times that of a normal desktop 8 core processor), an integrated 9.2 billion transistor, 5.2GHz frequency, and 128KB L1 data cache, 128KB L1 instruction cache, 4-4MB L2 eDM cache, and 256 L3L3.
The latest Power 9 single-core performance increases by 10%, multicore increases by 20% (from 10 to 12 cores), L2 cache increases by 33%, L3 cache doubles, L4 cache increases by 43%, all under the same 14nm SOI process.
IBM recently released the Power ISA 3.1 instruction set, introduced a new instruction prefix format, added BF16 support, and added a number of new instructions, mainly to enhance AI and high-performance computing power, and extend support for more data types.
The first processor to use the Power ISA 3.1 instruction set will be Power 10, which is expected to be officially unveiled at the Hotchips 32 conference in mid-August, and the process should be upgraded to 7nm, the core number will continue to rise, and pcIe 5, DDR5, etc., after all, power 10-based systems will not be available until 2021.