Small chips continue to receive market attention, but there are still some challenges to get more widespread attention and support. AMD, Intel, TSMC, Marvell and others have developed or rolled out devices using the advanced design approach of small chip models. But the adoption of small chips has been limited in the industry because of the lack of ecosystem support. In response to these problems, solutions have been proposed, and generation factories and OASTs (companies that carry out IC packaging and testing) are making small chips to drive the entire industrial chain.
For small chips, the main goal is to reduce product development time and cost by integrating the originally produced chip into a single circuit board. Therefore, a chip manufacturer may have a library of modular chips or small chips. Small chips can be chips made from different process nodes, and customers can mix and match small chips and connect them with die-to-die interconnect schemes.
Small chips are not a new concept. Over the years, some companies have introduced designs similar to small chips, and the model is getting more and more attention. In general, the industry develops an On-Chip System on SoC, where each module needs to use the same advanced manufacturing process and packaging, but this approach is becoming more complex and expensive as advanced process nodes become more complex and expensive.
Some companies continue to move on this path, but many are looking for other ways. Another way to develop system-level design, with advanced package combinations of complex chips, small chips are one way to modularize chips.
“We’re in the early stages, and Intel and other similar products will reflect this development. Each major foundry has its own technical road map to increase the density of interconnects, including 2.5D and 3D,” said Ramune Nagisetty, Intel’s director of process product integration. “In the next few years, we’ll see small chips implemented in 2.5D and 3D packages, and we’ll see them expand into logical memory and logical stacks.” “
Intel and a few other companies have the technology to develop these products, but many companies don’t yet fully own them, so that they need to discover them and find ways to use them, so they face some challenges:
The ultimate goal is to obtain high-quality, interoperable small chips internally or from multiple other vendors, a model that is still under study.
Third-party die-to-die interconnect technology is on the rise, but it’s not enough.
Some die-to-die interconnect schemes lack design support.
Foundry and OSAT will play a major role, but finding suppliers with IP and manufacturing capabilities is not easy.
The current work is to overcome these challenges, and over time, small chips will continue to evolve. It won’t replace traditional SoCs, and no technology can meet all of your needs, so there’s still room for multiple architectures, and many people won’t develop small chips.
Applications and challenges for small chips
For decades, chipmakers have followed Moore’s law of doubling chip performance every 18-24 months, where suppliers have introduced chips based on the latest technology to develop devices with higher transistor densities and lower prices.
This law no longer applies from 16nm/14nm. The cost of designing and manufacturing integrated circuits skyrocketed, and the pace of the overall upgrade nodes began to increase from 18 months to 2.5 years or more. Of course, not all chips require advanced nodes, and not all components currently on the same chip benefit from scaling.
The advantage that small chips can play is that a larger chip can be broken down into many smaller chips and combined and matched as needed, and the small chip can be cheaper and have a higher yield than an integrated chip.
Small chips are not package types and are part of packaging (packaging) technology. The core can be integrated with small chips into existing package types such as 2.5D or 3D, fan-out or multi-chip modules (MCMs). Some people may use small chips to develop new architectures.
All of this depends on demand. “It’s an architectural approach,” says Walter Ng, vice president of business development at UMC. It is a solution and cost solution that optimizes silicon for the required tasks, all in terms of performance, including speed, power, and cost, depending on the approach we take. “
There are other different approaches, such as Intel’s introduction last year of a 3D CPU platform using a small chip approach called Foveros. The package combines a 10nm processor core with four 22nm processor cores.
AMD, Marvell and others have developed similar chip products. Typically, these designs are designed for the same applications as today’s 2.5D packaging technologies, such as AI and other data-intensive workloads. “Logic/memory on the mediation layer is probably the most common implementation today,” says Intel’s Nagisetty. In high-performance products that require a lot of memory, we’ll see how to use a small chip-based approach. “
However, small chips will not dominate. “The type and number of devices is increasing,” Nagisetty said. I don’t think all products will adopt a small chip-based approach. In some cases, a monochip mold will be the lowest cost option. But for high-performance products, it is safe to say that the small chip method will become a specification, although the technology is not yet mature. “
Intel and other companies are ready to develop products. Typically, to develop small chip-based products, you need to use well-known bare chips, EDA tools, die-to-die interconnect technologies, and manufacturing technologies.
“If you look at who’s doing small chip-based designtodaytodaytoday, they’re often vertically integrated companies. They have all the internal components,” said Eelco Bergman, ASE’s senior director of sales and business development. “If you want to ‘stitch’ a few chips together, you need to have a lot of detail about each chip, its architecture, and the physical and logical interfaces on those chips.” You need EDA tools that can link the common design of different chips. “
Not all companies have internal components, some are available, and others are not ready. The challenge now is to find the necessary parts and integrate them, which will take time and resources.
“Small chips seem to be the hottest topic right now. The main reason is the diversity of applications and architectures required by the edge,” said Scott Kroeger, Veeco’s chief marketing officer. “If used correctly, small chips can help solve this problem. There is still a lot of work to be done, and the main question is how to integrate different types of chips into a single device. “
Where do you start? For many design services companies, foundry and OSAT may be the starting point. Some foundrys not only work for foundry, but also provide a variety of packaging services, including OSAT packaging/assembly services.
Some companies are already preparing for the era of small chips. TSMC, for example, is developing a technology called Integrated Chip System (SoIC), which allows small chips to provide customers with a 3D-like design, and TSMC has its own die-to-die interconnect technology (Lipincon).
Other foundry and OSAT offers a variety of advanced package types, but they have not developed their own die-to-die interconnect solutions. Instead, the foundry and OSAT are working with organizations that are developing third-party interconnect solutions, and this work is still ongoing.
Interconnection is critical. Die-to-die’s interconnect encapsulates one piece of bare metal with another, each containing an IP module with a physical interface, and a bare sheet with a common interface that can communicate with another piece of bare metal over a short distance of wire.
Many companies have developed interconnects with proprietary interfaces, which means they can only be used for the company’s own devices. However, in order to expand the adoption of small chips, the industry needs to use open interfaces to interconnect so that different chips can communicate with each other.
“If the industry wants to move toward supporting a small chip-based ecosystem, it will mean that different companies have to start sharing chip IPs with each other,” says Bergman of ASE. There is a solution to this obstacle. Replace shared chip IP with an integrated standard interface. “
To that end, the industry is learning from the DRAM business. DRAM manufacturers use the standard interface DDR to connect chips in the system. “I don’t need to know the details of the storage device design itself, I just need to know what the interface looks like and how to connect to my chip. Bergman said. “When we started talking about small chips, the same was true. The idea of reducing ip sharing barriers can be expressed as: let’s move in the direction of some common interfaces so that I know how my chip and your chip are connected together in a module, similar to LEGO’s modular approach. “
Find a standard interface
Happily, some companies and organizations are developing open die-to-die interconnect/interface technologies. These technologies include AIB, BoW, OpenHBI, and XRS. Each technology is at a different stage of development, and no one technology can meet all needs, so there is room for other options.
The Advanced Interface Bus (AIB), developed by Intel, is a die-to-die interface scheme that transmits data between small chips. There are two versions of this scenario: AIB Base for “lighter applications” and AIB Plus for higher speeds.
The AIB does not specify a maximum clock rate and the minimum clock rate is very low (50MHz). AIB has a high bandwidth, with a typical data rate of 2G per second per line. David Kehlet, an Intel research scientist, said in the white paper. Intel also owns a small commercial contract business and a key internal packaging division.
At the same time, the Optical Connectforum is developing a technology called CEI-112G-XSR. XSR provides 112Gbps core-to-core connectionpers per channel for ultra-short and ultra-short distance applications. XSR connects small chips and optical engines in the MCM. Applications include AI and networks. The final version of the XSR standard is expected to be released by the end of this year.
The Open Domain Private Architecture (ODSA) team is defining two additional core-to-core interfaces: The Electrical Harness (BoW) and OpenHBI. BoW supports both general and advanced packages. Ramin Farjad, Marvell’s Chief Technology Officer for Network/Automotive Technology, said in a recent presentation: “The initial goal was to provide a common die-to-die interface that could be used in a variety of package solutions. “
BoW is still in development, with both termination and non-termination versions. BoW has a chip throughput of 0.1Tbps / mm (simple interface) or 1Tbps / mm (advanced interface) with a power efficiency of less than 1.0pJ / bit.
At the same time, Xilinx suggests that OpenHBI is a die-to-die interconnect/interface technology derived from high-bandwidth memory (HBM). HBM itself is used in high-end packages. In HBM, DRAM bare chips are stacked together to achieve more memory bandwidth in the system. The physical layer interface routes the signal between the DRAM stack and the SoC in the encapsulation. The interface is based on the JEDEC standard.
OpenHBI is a similar concept. The difference is that the interface provides a connection from one small chip to another in the package. It supports intermediary layers, fan-out and small-spacing organic substrates.
“We’re trying to use the proven JEDEC HBM standard,” Kenneth Ma, Xilinx’s chief architect, said in a recent speech. Try existing and proven PHY technologies and further optimize them. “
The OpenHBI specification has a data rate of 4Gbps, a latency of 10ns, and a power efficiency of 0.7-1.0pJ/bit with a total bandwidth of 4,096Gbps. The draft is scheduled for release at the end of the year. The next version of OpenHBI3, which requires data rates of 6.4Gbps and 10Gbps and latency of less than 3.6ns, is also being developed.
Ultimately, customers will be able to choose from several die-to-die interconnect/interface options, but this does not solve all the problems. The interoperability of small chips from different companies is still in its infancy. There are real challenges in interoperability, which is why we haven’t seen a lot of interoperable small chips yet,” says Intel’s Nagisetty. “There’s also the question of business models. How do we manage risk when we get chips from start-ups? For example, if those cores fail after encapsulation or other steps, what should be the risk management model? There is a lot of complexity and supply chain management. It requires a new level of complexity in the supply chain. “
Given these problems, some customers may think that small chips are not worth it in the long run. Instead, customers may end up using OSAT or foundry to develop more traditional premium packages. “In the packaging industry, many people may end up following our path because it’s easier to re-integrate packaging,” said Ron Huemoeller, Vice President of Research and Development at Amkor. “
“The bus type of die-to-die is usually defined by our customers, not by Amkor or OSAT. The available interfaces, such as AIBs and Electrical Harnesses (BoWs), are constantly working to make common specifications available for the die-to-die interface, thus contributing to the overall small chip market. Customers can choose to use open standards or retain proprietary interfaces. Currently, we see a mixture of the two approaches in our customer base. Huemoeller said.
“It is worth noting that die-to-die interfaces cover two broad categories, from single-ended broadband buses such as HBM data buses to serialized interfaces with few physical lines but higher wire speeds. Performance trade-offs, including latency, power consumption, and physical lines, are considered in all cases, which can affect the choice of package technology. From a packaging perspective, bus type and physical line density will drive the choice of package solution. Typically, you choose a module type with a higher line density (2.5D or high density fan-out on the substrate) or a MCM on a classic high density package substrate. “
To address many of these issues, ODSA is developing a chip market called Chiplet Design Exchange (CDX). The purpose of CDX is to establish an open format to ensure the secure exchange of confidential information. It will also have reference workflows that demonstrate the flow of information about the prototype. Bapi Vinnakota, the sub-project leader for OSDA, said. CDX attracts a wide range of companies, including EDA suppliers, OSAT, design services companies, small chip suppliers and distributors. CDX has conducted research on power estimation and testing of small chips. It is building a small chip catalog and will develop a prototype of the packaging. “
The timing of the CDX is unclear. At the same time, customers need EDA tools to design products that support small chips. These tools can be used in advanced packaging and small chip technologies, but there are still some gaps.
For small chips, it requires a common design approach. “The use of small chip-based decomposition design requires IC, packaging, and board-related functionality,” says John Park, Cadence’s head of product management. The transition to a chip-based approach presents new challenges for both chip designers and package designers. For packaging designers, the layout and validation of silicon substrates presents new challenges. Requirements such as layout, schematics, and smart metal balancing are common for IC designers, but these are new concepts for many packaging designers. “
Fortunately, EDA vendors offer cross-platform tools. Even so, there are still some challenges. “For example, when it comes from designing a single device to designing and/or integrating with multiple devices, the requirement to define and manage top-level connectivity becomes critical,” Park says. “Testing is another area where significant changes occur when designing multiple small chips in the 3D stack. For example, how do I test a small chip at the top of the stack that may not have any connection to the outside world? “
There are other questions. “To achieve a good economy of scale, we want small chips to be easily reused in many different packages,” said John Ferguson, director of product management at Mentor, a Siemens business unit. But this requires some rigorous documentation, and the accepted standards are observed, both throughout the industry, throughout the company. Without it, each design would continue to be a time-consuming, cumbersome and expensive custom project. “
But there are still some problems. For example, there is little design support for ODSA’s BoW and OpenHBI interfaces. To this end, ODSA is developing reference designs and workflows.
Design support for ODSA development does not seem to be a problem. “There are no major difficulties, even tool enhancements, for physical verification,” Ferguson said. Once the requirements and criteria have been identified, they will simply be properly implemented as rule constraints in a typical DRC or LVS card group. “
Making small chips
After the design is developed, it is done in the fab and then tested. The test unit consists of an automatic test device (ATE), a probe, and a probe card with a thin needle, which has a custom pattern designed for the wafer.
The detector takes out a wafer and places it on the chuck. It aligns the probe card with a lead bond pad or tiny bump on the chip. ATE conducts electrical tests on the chip.
“Testing and probing small chips presents huge technical and cost challenges,” said Amy Leong, senior vice president of FormFactor. “The new technical challenge is the need to significantly reduce the packaging bump spacing and size. Microconvex points can be as small as 25 m or less. In addition, the density of the microconvex pattern is 2-4 times that of the equivalent monocontroller. Therefore, the aiming accuracy required to detect such a small feature on a 300mm wafer is equivalent to positioning the nail head on a football field. “
Testing each microconvex is often expensive and impractical. “The cost challenge is how to intelligently execute KGD and provide good enough test coverage at a reasonable cost. Test design, built-in self-testing or test process optimization are important tools for achieving cost-effective testing strategies. Leong said.
Finally, cut the chip into small squares. In the package, the core is stacked and connected via a miniature convex, which provides a small and fast electrical connection between different chips.
Using a wafer bonding machine to snap a tube core is a slow process with some limitations. The state-of-the-art micro-convex spacing is 40?m. If you use today’s bonding machines, the industry can scale the convex spacing to around 10?m or 20?m.
The industry needs a new technology, copper blending. To do this, a dielectric-to-dielectric bonding chip or wafer is used, and then a metal-to-metal connection is made. For chip stacking, hybrid bonding is challenging, which is why it is still in the research and development phase.
There is another problem. In a polygrain package, a bad grain can cause the entire package to fail. John Hoffman, engineering manager at CyberOptics, said: “Small chip methods or various heterogeneous integration methods involve complexity, which drives the need for effective checks on high yields and long-term reliability. “
Obviously, the development of small chips faces some challenges, but the technology is also necessary. With chip scaling, a single chip can be retained, but few companies can afford advanced nodes.
The industry needs different choices, traditional solutions sometimes not meet these choices, but small chips offer a variety of possibilities and potential solutions.