Intel 10nm full line introduces new instruction set: cache efficiency soars

Intel today released the 39th version of its instruction set extension reference guide, revealing that the next 10nm family will introduce a new instruction set called CLDEMOTE, with a focus on improving cache efficiency and performance. The new instruction set, known as “Cache Line Demont”, meaning “cache line degradation,” allows the operating system to tell a processor core that if the specific content in the cache line does not need to be too close to the processor core, it can be moved to the cache away from the core, but not into the system main memory.

That is, if some of the data in the primary cache is not currently needed by the processor, it can be transferred to the second- or even third-level cache, and if there is similar data in the secondary cache, it can be transferred to the third-level cache.

As a result, the pressure on primary and secondary caches can be greatly reduced, and they can store much-needed data more efficiently with smaller capacities, closer to processor cores, and faster.

In addition, the first and second level of caching is exclusive to each core, the third level of caching is all core sharing, put some of the appropriate data in the third-level cache, in fact, more conducive to multi-core sharing.

Intel 10nm full line introduces new instruction set: cache efficiency soars

The CLDEMOTE directive supports a wide range of technologies, one is Sapphire Rapids, which is the next generation data center after 14nm Cooper Lake, 10nm Ice Lake, and the 10nm process with a new architecture.

The second is Alder Lake, the next generation of desktop Core after Comet Lake and Rocket Lake, also a 10nm process, with the CPU architecture expected to be Willow Cove.

The three are the core of the Tremont architecture for a low-power product line, including hybrid packages such as Atom Atom, Pentium, Celeron and even Lakefield.

Intel 10nm full line introduces new instruction set: cache efficiency soars