A new patent filed by AMD indicates that they are considering following Intel and Arm on the path to hybrid computing. But interestingly, this patent describes a very familiar product… Hybrid computing is when a processing device uses two (or more) different architectures and is optimized for different purposes. In this case, AMD wants to create a more power-saving laptop CPU/APU without sacrificing functionality.
To do this, they used a “high-function processor” that can do everything quickly, while a “low-function processor” does a few things very efficiently, all in a single CPU/APU.
The patent deals primarily with the basics of mixed computing. “When high-function processors are underutilized, heterogeneous processor systems transition to low-power mode by switching thread execution to low-function processors. This execution of the switch includes migrating data…” and then, “… When low-function processors are overused, heterogeneous processor systems transition to higher power mode by switching the execution of one thread. “
Intel’s Lakefield architecture does much the same thing: Intel uses four 10nm Tremont cores as low-function processors and one 22nm Sunny Cover processor as a high-function processor.
Arm has a similar design, such as the octa-core processor used in smartphones that specializes in high-performance tasks, while the other four cores manage background applications and connectivity.
One of the novelthings about AMD patents is their discussion of different implementations. The patent presents two alternate configurations. In the first case, the physical storage shared by the two processors is used for communication between the two. In the second case, a virtual link is created in the cache.
Here’s an example procedure in which a low-function processor (first processor) uses the first configuration to send instructions to the high-function processor (second processor).
The first processor executes a thread in low-power mode – The first processor detects that the thread is trying to take advantage of unsupported features . . . the first processor stops executing the thread . . . the first processor instructs the switch to the second processor and saves the thread state – the second processor resumes the thread state from the shared memory location and starts executing.
For example, this scenario might occur when a user has the processor decode the video stream after arriving at the Twitch home page. In this scenario, the high-function processor is (or may have been) active;
Patents do not indicate a company’s willingness to enter the market, and a fairly casual patent like this certainly does not confirm any attributes of a future product. But overall, AMD’s pursuit of the mobile market is becoming more and more feverish, and it’s interesting to be aggressive against Intel in another area.