Intel 10nm++ Tiger Lake Cache resign: Capacity Increases

Over the years, Intel processor processes and architecture innovations have accelerated, and after the 10nm (exactly 10nm plus) Ice Lake 10th Generation Core, Tiger Lake, which will be introduced next year, will be 11th generation Core, if not unexpected. Tiger Lake has changed dramatically, with the CPU architecture upgraded to Willow Cove in addition to process updates, the core display architecture upgraded to the 12th generation, and xe, which is the same as discrete graphics cards, supporting new display, video technology, and I/O interfaces.

Intel 10nm?Tiger Lake Reset Cache: Capacity Increases

For the first time in the GeekBench 5 test database, a Tiger Lake prototype platform, “Corktown”, is exactly the ultra-low power Tiger Lake-Y, 4 core 8 threads, and the most surprising thing is the redesign of the cache structure and a significant increase in capacity.

Of these, the first-level data cache for each core is 48KB and the first-level instruction cache is 32KB, which is exactly the same as Ice Lake, while the second-level cache comes to 1280KB (four cores is 5MB), which is 1.5 times larger than Ice Lake 512KB, if compared to Skylake 256KB is a full five times.

The total amount of the three-level cache is 12MB, or 3MB per core, which is also 50% larger than previous exposure.

The performance gains of a larger multi-level cache, supplemented by a reasonable hierarchy, high speed, and low latency, will definitely be significant, both in everyday applications and in gaming.

Tiger Lake will also support the next generation of LPDDR5 low-power memory and continue to fully support the AVX-512 instruction set, according to previous reports.

However, Tiger Lake currently only knows that there is a low-power version of the Tiger Lake-U series, the Tiger Lake-Y series of ultra-low-power versions, are for mobile platforms, and what is on the desktop is still very vague, anyway Intel has vowed that 10nm will not miss the desktop.

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