In the world of computer chips, many parameters are “the bigger the better”. For example, more cores, higher GHz main frequencies, and greater floating-point computing power. The difference is that the industry is pushing towards a smaller goal in the process. From 10nm to 7nm up to 5nm and smaller scales. But before we dive into why, we need to review the processor architecture and how engineers plan and design the chip.
(Instagram from TechSpot)
Now: This article focuses on how computer chips are physically assembled, and the lithography parts involved in manufacturing are brief.
In the chip industry, feature size is closely related to process nodes, and the details can be referred to in the third chapter of How to Design THE CPU.
Each execution unit within the chip can perform mathematical operations and data storage, and its performance is quite dependent on the power-of-work process node (specifically every iteration of the same manufacturer).
In marketing practice, however, the term is still fairly loose, depending on the minimum, or average, value sitter between transistors that manufacturers prefer.
In the processor world, no change will happen overnight. Larger components mean longer periods of time to change their state, longer propagation times for signals, and more energy to consume, not to mention larger chips taking up more physical space.
The image above shows Intel’s three old CPUs, the far left is the 2006 Cyyoungs, the 2004 Pentium Mobile Processor in the middle, and the old collapse processor of 1995.
The three chips have process nodes of 65, 90, 350 nm , 24 years ago, and have five times the volume of their key components as they were 13 years ago.
At the same time, there are about 290 million transistors inside the newer CPUs, compared with only one percent of the old collapse (slightly more than 3 million). In terms of power consumption, the 2006 Celeron processor has a TDP of about 30W and the old Pentium is only 12W.
The increase in thermal design power consumption is mainly due to the flow of electrical energy around the circuit in the chip, energy loss due to various processes, most of which is released in the form of heat. Although 30W is several times more than 12W, the transistors of the new CPU are nearly 100 times higher than the old chips.
That’s why smaller process nodes allow the chip to switch transistors smaller, switch transistors faster, increase computing per second, and reduce lost energy consumption (heat).
(Pictured: Peellden, Wikimedia Commons)
So why don’t we “step in” and directly allow all chips to use the smallest process? Speaking of which, it is necessary to mention the production process known as “lithography”.
The light mask blocks light from certain areas, and the light allowed to penetrate is concentrated at a small point and then reacts with a special layer used in chip manufacturing to determine the location of the parts.
You can imagine taking an X-ray of your arm, the bones blocking the light (which acts as a light mask), and the muscle tissue allowing X-rays to penetrate to get an image of the internal structure. The iteration of the lithography process is related to the wavelength of light.
(Pictured: Philip Ronan, Gringer)
Visible light (380 to 750 nm) is only part of the spectrum, and radio waves, microwaves, X-rays, etc. You can see the size of the light wave in the image above, about 10?-7 meters (about 0.000004 inches).
In the words of the story, we continue to talk about the manufacturing process of the chip, such as the old Celeron using a 65nm process node. So how do we make parts that are smaller than light waves? The answer is to use ultraviolet (EV), or even ultra-uv lithography (EUV).
In the spectrogram, the UVs start at around 380nm until about 10nm. Manufacturers such as Intel, TSMC, Grofonded, etc. have now touched extreme lyuvno (around 190 nm).
The new process not only makes the components themselves smaller, but the overall quality may also be better, thus encapsulating the individual parts tightly together, helping to reduce the overall size of the chip.
(A close-up of manufacturing defects, from Solid State Technology)
Different enterprises have different claims about the size of process nodes. For example, Intel uses the P1274 to refer to the current 10nm process, which TSMC calls 10FF.
After selling Grofond, AMD is now relying on TSMC contracts and using a 7nm production process. It is important to note that although some of the smallest features span only 6nm, most of the other features are slightly larger than this.
In order for ordinary people to understand how small 6nm is, it must be mentioned that the diameter of the silicon atom itself is about 0.1nm, while the spacing of most of the silicon atoms that make up the processor body is only 0.5nm. In other words, a single transistor covers fewer than 10 silicon atoms in every way.
Putting aside the incredible facts, EUV lithography technology still raises many serious engineering and manufacturing challenges. Intel has been working hard to bring its 10nm capacity to 14nm, and Grofont earlier last year stopped developing 7nm and below.
The problem is that as the electromagnetic wavelength gets shorter, it carries more and more energy, leading to a greater potential for damage to the chip being manufactured. In addition, small-scale manufacturing is highly sensitive to contamination and defects in the materials used.
Other problems include diffraction limits and statistical noise( natural variations in the energy efrom eUV waves deposit into the chip layer, resulting in manufacturers unable to meet 100% perfect chip manufacturing targets.
Another problem is that in the weird atomic world, we can no longer assume that current and energy are transmitted and follow the rules of classical physics systems. When you move electronics, you encounter more difficult problems.
In the case of Intel and TSMC, achieving this goal will become more difficult because the insulation is not thick enough. However, the current production problems, almost all concentrated in the EUV lithography technology inherent defects.
That’s why we’ll have to wait years to see if quantum processing is more advantageous. In addition, for commercial reasons, smaller processes can save more.
If Intel used the 28nm process to manufacture Haswell series CPUs, such as the i7-4790K, the cost would double. But by cutting out more chips on a single wafer, the extra costs can be largely offset.
Over the past few years, chip applications, represented by smartphones and household/cars, have seen near exponential growth. Chipmakers are also forced to bear the financial losses caused by the shift to smaller process nodes until industries that can mass-produce at large-scale levels are more mature.
While Grofond’s abandonment may sound pessimistic, Samsung and TSMC are somewhat pleased with the 7nm input/output. AMD’s newly released three-generation Ryzen CPU, for example, gives the market a shot in the arm.
This range of high-end PC processors uses TSMC’s 7nm process and combines a 14nm chip from Grofond. The former can be considered a traditional CPU part, while the latter is an SoC bridge component that integrates the DDR4 memory controller with PCI Express 4.0.
The figure above shows Intel’s process node changes over the past 50 years, with X-axis from 10 to 10,000 nm and Y axis from 1970 to 2020. Overall, the chip giant iterates about every 4.5 years.
If all goes well, it is expected to launch a 5nm product line by 2025 (hopefully 10nm capacity will not be delayed). Samsung and TSMC are also actively investing in 5nm research, and hopefully the industry will continue to surprise consumers.