Cas research and development of the world’s first layered vertical nano-ring gate transistor with self-aligned gate

At present, the world’s most advanced semiconductor technology has entered 7nm, the next step is to enter the 5nm, 3nm nodes, manufacturing more and more difficult, where the limitations of transistor structure is very important, the future process requires new transistors. Chinese scientists have developed a new type of vertical nano-ring transistor that is considered a major technical candidate for processes 2nm and below, according to the Chinese Academy of Sciences.

Since Intel’s first 22nm FinFET process, the world’s leading semiconductor manufacturers have started to enable FinFET fin transistors at 22/16/14nm nodes, and will continue to use finFET transistors in the future at 5nm, 4nm and other nodes, but the nodes after 3nm and later will change, and Samsung was the first to announce last year that 3 nodes will switch to GAA surround gate transistors.

Based on the new GAA transistor structure, Samsung has created MBCFET (Multi-Bridge-Channel FET, multi-bridge-channel field effect tube) using nanochip devices, which can significantly enhance transistor performance, replacing FinFET transistor technology, officials said.

In addition, MBCFET technology is compatible with existing FinFET manufacturing processes and equipment, thus accelerating process development and production.

Not long ago, Samsung also announced specific indicators of the 3nm process, compared with the current 7nm process, the 3nm process can reduce the core area by 45%, reduce power consumption by 50%, and improve performance by 35%.

From the above information can also be seen the significance of GAA surround gate transistors, and the Chinese Academy of Sciences Microelectronics Leading Center Zhu Huixuan researcher and his team recently broke through this field, officials said they have been from 2016 on the relevant basic devices and key processes to carry out systematic research, The world’s first layered vertical nano-ring transistor (Vertical Sandwich-All-Around FETs or VSAFETs) with self-aligned gate is proposed and realized, and has been granted a number of patents for Chinese and American inventions.

The findings were recently published in IEEE Device Letters, the world’s leading journal in microelectronics (DOI: 10.1109/LED.2019.2954537).

Cas research and development of the world's first layered vertical nano-ring gate transistor with self-aligned gate

Top left: STEM top view, made with atomic layer selective etching of silicon niobium silicon method 10 nm wire (left) and 23 nm thick nanochips (right)

Top right: TEM profile (left) and HKMG local amplification with layered vertical nano-ring gate transistors (VSAFETs) with self-aligned high k metal grate

Below: Structure and I-V characteristics of pVSAFETs devices: device structure schematic (left), transfer characteristic curve (middle) and output characteristic curve (right)

According to the introduction, Zhu Huixuan team systematically developed a method of selective etching of niobium silicon in atomic layer, combined with multi-layer extension growth technology, this method is used for selective etching of silicon/silicon super-crystal line layer, so as to accurately control the size of nanotransistor grooves and effective gate length; The team finally produced a p-type VSAFET with a gate length of 60 nanometers and a thickness of 20 nanometers. The prototype devices have SS, DIBL, and current switch ratios (Ion/Ioff) of 86mV/dec, 40mV and 1.8×105, respectively.

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