Lakefield will welcome the Refresh version next year and may directly integrate the 5G baseband in the future

Lakefield is Intel’s new size and core hybrid processor and the first x86 processor to adopt a “hybrid architecture.” It uses Intel’s latest Foveros packaging process, Intel’s exclusive 3D stacking packaging process, which reduces the entire package size while providing ultra-high bandwidth for the interconnection between Die. So far, two products have announced they will use the Lakefield processor, Samsung’s Galaxy Book S and Microsoft’s Surface Neo, both of which will be available next year. But Intel recently revealed on IEDM 2019 that the Lakefield processor could be available next year.

Lakefield will welcome the Refresh version next year and may directly integrate the 5G baseband in the future

On IEDM 2019, Intel engineers told AnandTech that the Lakefield version would be available by the end of 2020, and he said the first-generation Lakefield processor was now available, but that’s something that our average consumer would not be able to get. This point in time coincides with the launch of the Surface Neo, and chances are that we can see the Refresh-passed hybrid processor directly above the Surface Neo.

So what would it “Refresh” do? Because the Foveros process has a very high degree of flexibility, the components above the processor are likely to be minorly upgraded, such as small computing core upgrades or I/O minor upgrades. And given Intel’s recent announcement of collaboration with MTK on 5G technology and products, coupled with the Foveros stacking process, it’s entirely possible to see an x86 processor with an integrated 5G baseband, which could also be the definition of “Refresh.”

Another product that will use the Foveros packaging process will be the yet-to-be-released Xe GPU, and its HPC version will use Foveros to scale up its computing to better accommodate HPC’s use. In recent years Intel has introduced a number of leading packaging technologies, and in the post-Moore Law era, when process processes can no longer effectively drive chip size increase, better packaging processes will be more useful, it can help achieve greater computing scale.

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