WD announces new SweRV core design based on RISC-V

WD dhas just added two new members to its own SweRV microcontroller CPU portfolio, SweRV Core EH1 and SweRV Core EL2. Like its previous generation, the company provided the industry with a free register transfer-level (RTL) design abstraction, introduced the first hardware reference design for OmniXtend cache consistency memory based on an Ethernet protocol, and transferred management and support for the architecture to chips Alliance.

Western Number announces new SweRV core design based on RISC-V

(From: WD, via AnandTech)

It is reported that SweRV Core EH2 appears to be used for the 32-bit ordered core of the microcontroller, using a 9-stage pipeline s2-way over-quantity design, and supports simultaneous multithreading.

In short, EH2 is a performance-enhancing version of EH1 launched last year, supporting SMT, built using TSMC’s 16nm FinFET process for optimal PPA (power, performance, and area) efficiency.

Western Number announces new SweRV core design based on RISC-V

SweRV Core EH2 will still use the same areas as EH1, such as the master of SSDs. Based on the simulation results of The West Number, the EH2 core delivers 6.3 CoreMark/MHz performance, which is higher than the 4.9 CoreMark/MHz of EH1.

The size of the EH2 (based on the 16nm process) is only 0.067 mm2, which is significantly improved from 0.11 mmper (based on 28nm) of EH1.

Western Number announces new SweRV core design based on RISC-V

In contrast, SweRV Core EL2 is designed to be miniaturized to replace the required smaller possible sequential logic and state machines in the controller SoC.

The EL2 itself is a 32-bit ordered core with a 1-road sign volume and a four-stage pipeline design. The western number represents an EL2 core area of 0.023 mm2, resulting in 3.6 CoreMarks/MHz performance.

Western Number announces new SweRV core design based on RISC-V

All three SweRV cores will be available in the near future for a variety of products in The Western Number. At the same time, the company hopes that they will benefit and enrich the RISC-V ecosystem.

Western Number announces new SweRV core design based on RISC-V

At the same time, West shows the hardware reference design of its first OmniXtend cache-consistent memory based on the Ethernet-compatible structure protocol to make it easier for chip developers to embed it in their designs.

Western Number announces new SweRV core design based on RISC-V

Initially, the architecture will be used for persistent memory connected to the CPU, but can also be integrated into components such as GPUs, FPGAs, machine learning accelerators, and so on. Interested friends can get it from Chips Alliance, which will also be responsible for further development of the OmniXtend protocol.

Add a Comment

Your email address will not be published. Required fields are marked *