For Intel, many players expect both its new process to move forward and a strong new architecture to change the current recurrent situation. Today’s emergence of a new U, can not be unable to make people think. The SiSoftware database lists one of The Vyco’s servers/workstations, X12DAi-N SMC X12, using two Intel processors, but does not identify specific models, but the general landmark is Core i3/i5/i7, all of which are 6 core 12 threads with a main frequency of 3.0GHz.
It’s very special and weird to have caches, especially with secondary cache capacity of 1.25MB per core (9MB in total), which is unprecedented.
You know, the Skylake family until the ninth generation Core is a core 256KB secondary cache, the latest ten generation Core Ice Lake only increased to 512KB, and the Core X series is 1MB, is already the largest of the existing products, and this 1.5MB is clearly not the total amount of secondary cache (can not be divisible by 6 )。
Closest to this is the next-generation mobile platform, 10nm Tiger Lake, where exposure shows that the secondary cache increased to 1.25MB per core, still a little bit worse.
But strangely, the new U’s three-stage cache is small, with only 9MB, comparable to the nine-generation Core.
The impact of cache capacity on architectural design and performance is enormous, and the differences can be two very different architectures (AMD Zen, Bulldozer) or two different structures that share core designs and are completely different from the periphery (Intel Skylake, Skylake-X).
Intel’s next product plans are quite large, with 14nm Comet-S, 10nm Tiger Lake, 14nm Rocket Lake, and more, and 14nm Cooper Lake, 10nm Ice Lake, 10nm Sapph ire Rapids.
As for this special new U in the end which platform, it is really difficult to say, since the two-way parallel basically can exclude the consumer level, and to be sure, the architecture did make a drastic redesign, this alone is worth looking forward to.