TSMC turns to 3nm for higher performance

As designers prepare for the upcoming 5nm and 3nm nodes, the bigger challenge is imminent. The miniaturization of equipment on modern integrated circuits poses challenges for circuit designers dealing with power and ground networks (PDNs). The past decade has witnessed the rise of FinFET devices with higher drive strength than previous flat devices.

The use of FinFET devices increases the drive strength per unit area, which means higher current density and greater current transients. This trend has led to the chip becoming more sensitive to fluctuations in the supply voltage, which exacerbates the power integrity challenge slotted up in system design. Circuit designers rely on decoupling capacitors as a basic tool for reducing PDN impedance, suppressing noise and improving overall PI through decoupling or bypass circuits or parts of interconnects. For signals, noise from the interconnect can be diverted by decoupling capacitors and then passed to another circuit. But to do this, you must control the parasitic resistance and inductor, which usually means that the decoupling capacitor must be physically close to the desired circuit.

TSMC’s primary package for high-performance computing applications is CoWoS (Chip-on-Wafer-on-Prime). This 2.5D wafer system integration is used to effectively integrate multiple pieces of bare (Die) into the silicon mediation layer. The use of silicon enables very fine submicron interconnects. In addition, it can use smaller microconvexes, allowing for higher signal density and higher bandwidth at lower per bit energy, which is ideal for high-performance chips. CoWoS is widely used in products including GPUs, CPUs, vector processors, neuroprocessors and programmable switches.

Intel Barefoot Tofino 2 is a CoWoS-based product that combines 7nm logic with HBM2 memory

To help reduce signal noise and ensure stable voltages, TSMC uses silicon substrates already present in the package to implement high-density metal-insulator-metal (MiM) decoupling capacitors that may be used to replace or assist certain capacitors. Largediscrete MLCC components, otherwise they must be installed on the top.

TSMC introduced the new HD-MiM on IEDM 2014. High K MiM is inserted between Metal1 and Metal 2 layers of the Si mediation layer. Because they are located in the inserter, they can be used effectively for system-level decoupling applications. In time, the decap combination of 1, 2 and 3 in series is discussed, providing capacitors of 17.2, 4.3 and 1.9 fF / ?m2, respectively. With HD-MiM, HD-MiM can provide a total capacitance of approximately 3.5?F for plug-in chips over the entire capacitor area of 200mm2.

Dig a deep trench

The high-performance circuits of the future require better decoupling capacitors to mitigate sagging and absorbing transients. At the 2019 IEDM earlier this week, TSMC launched iCAP. iCAP takes a very different approach – TSMC chooses a vertical deep groove rather than a horizontal line. TSMC first adopted this approach a few years ago, when Apple introduced the A10 processor, which uses inFO packages and Through InFO Via (TiV). TSMC has replaced MLCC LSC and similar components with DTCTPs there in order to significantly increase possible capacitance density.

Because tsv and DTCs exist on the same silicon chip at the same time, there are two ways to build iCAPs. In the DTC-first method, deep grooves are formed prior to the TSV process, which means that special care must be taken to ensure that the TSV thermal budget does not affect The DTCs. In addition, in the TSV priority flow, the TSV structure is first formed using the standard TSV process, but special attention must be paid to mitigating TSV-related problems, such as through convex phenomena. As with the HD-MiMs, one of the main advantages of DTC package circuits is that they are free to be as close as possible to the desired circuit (similar to the on-chip package circuit), but the additional advantage is that deep grooves allow for higher capacitors. In addition, since this can be achieved in the entire 1700 mm2 layer, and the top of the layer has a wide variety of chips, the DTCs can be designed to better solve the PI problem of the chip above.

The iCAP standard unit is 40 sm x 40 sm. Although TSMC does not disclose the depth of the groove, it can achieve capacitance density of up to 340 nF /mm2. Capacitance density is nearly 20 times higher than HD-MiM. Because multiple iCAPs can be used on a single inserter, the total capacitance of each Si inserter is more than 68?F.


Both HD-MiM and iCAP have high yields and are reported to have a leak current of less than 1fA / ?m2, including at high temperatures. TSMC reported that iCAP’s improvement sprigto PDN was very good. Compared to coWoS-based equivalent designs without iCAP, the TSMC has only 0.05 times impedance and a voltage drop of 0.45 times.

Add a Comment

Your email address will not be published. Required fields are marked *