There are already many manufacturers working with ARM, such as Applied Micro/Ampere, Calxeda, Broadcom/Cavium/Marvell, Qualcomm, Huawei, Fujitsu, Annapurna/Amazon, and even AMD. Some of these designs have achieved initial success. At the same time, vendors decided to continue to push the Neoverse N1 new kernel family to more customers looking for high-performance and scale-up deployments.
(Image via AnandTech)
Amazon, for example, has brought Graviton 2 based on the N1 kernel to market. There is also a next-generation Ampere CPU for cloud services, codenamed QuickSilver, which is officially announced until the first quarter of 2020.
Earlier reported eMAG has enabled Ampere Computing with appliedMicro-derived custom ARM kernels.
It has been a great success among second-tier cloud providers, such as Packet, and cloud services for many Chinese Android smartphone game providers.
The company has yet to announce the official name of the new product, calling it “next-generation Ampere” or using the SoC code “QuickSilver.”
What we’ve been told is that the new product is based on Ampere’s new foundational design, is relatively independent of Applied Micro’s IP acquisition, and plans to compete with Graviton2 in Amazon’s cloud service (AWS) infrastructure.
The good news is that today we’ve learned some of the details, such as the exact SKU to be released, thermal design power consumption (TDP), frequency, and selling price.
The next generation of Ampere will be manufactured using the TSMC 7nm process, a single chip with 80 cores. Its ARM-based Neoverse N1 design connects to pairs of clusters via mesh IP (CMN-600) rather than custom production as eMAG.
The core is the same as Graviton2 and is expected to be optimized for power consumption, performance, latency, and throughput, bringing more cores and other features. It’s worth noting that N1 is a single-threaded kernel, not a multithreaded, and QuickSilver SoC was designed with containers in mind.
The chip will support container-level QoS instructions to avoid customer-specific consumption of shared resources and to ensure additional RAS capabilities to perform consistently.
Ampere notes that QuickSilver is designed to ensure consistency in multi-tenant environments until certain performance is required, indicating container-based frequency and cache control. To achieve this, the accelerated (Turbo) frequency of the new chip will be consistent.
In addition to 80 cores, QuickSilver will have 128 PCIe 4.0 channels. Although Ampere has not currently disclosed the exact number (until Q1 2020), it has been confirmed that it will have more chips than x86/ARM.
Given that AMD EPYC processors already offer 128 PCIe 4.0 channels, things will be more interesting if QuickSilver can provide more than 128, such as opening up more possibilities for accelerated/storage connectivity in specific markets.
Ampere is an important partner in Nvidia’s 2020 CUDA-on-Arm strategy, so we’re expected to access more Nvidia GPU resources with quickSilver cloud instances.
In addition, the new chip has 8 DDR4 memory channels and may exceed the frequency and capacity limits of DDR4-2666 on the current eMAG (e.g. support for DDR4-3200, and 2 DIMMs per channel).
Finally, Ampere wants to use the CCIX protocol on the basis of PCIe 4.0 to enable slot-slot communication and other related accelerator/storage layer accessories. Standardized care protocols are helping them speed up the time to market.