Over the next decade, the storage market will continue to strive for a balance of storage density, speed, and demand. Although the technical priorities vary from manufacturer to manufacturer, Kioxia (formerly Toshiba Memory) is not optimistic about the prospects for stacked storage solutions such as 3D XPoint. At this year’s International Electronics Conference (IEDM), the company announced the BiCS flash series and the upcoming XL-Flash technology, along with a slide show of vision for the future.
(Image via AnandTech)
Dynamic Random Memory (DRAM), Flash, and Storage Level Memory (SCM) are the three major trends currently on the market, and Kioxia also envisions intel and Micron’s long-term vision for 3D XPoint.
Flash floating and charge trap technologies have undergone many changes over the past few decades. The status of a newly developed memory depends on the resistance or spin of the medium in the unit, not the voltage.
Traditionally, it is easy to think of each cell as a “0” or “1” with a different value. However, as material types develop, each unit has been able to accommodate more states (SLC, MLC, TLC, QLC, etc.).
This makes it easy to achieve a doubling of capacity, but it also places higher demands on the accuracy of the detection circuit, often increasing the unit size or reducing the overall density.
Kioxia’s current BiCS flash technology relies on stacking multi-layer edgy floating grid units in towers and then repeating the design in the xy direction to increase capacity. The company currently offers a large number of TLC and QLC products and wants to create a 5-bit per unit for special applications.
The number of design layers in the BiCs family of products is also increasing, from 32 to 48 to 64 and 96, and is expected to add more than 128 layers in the future. The addition of layers is relatively easy compared to other methods.
Kioxia is also developing a new flash memory called XL-Flash. Traditional flash memory works as “pages” and “blocks”, while storage class memory works in “bits”.
This means that while DRAM can access each bit and modify it, in flash, this means that any write needs to be written to the entire page at once, and the write loss is multiplied.
3D stacked storage units work differently than flash memory, in the case of 3D XPoint, which uses phase-changing materials to change the resistance of the storage unit and can be accessed via an electronic selector switch.
Build memory by alternating the direction of the word and bit line to preserve the bit addressable nature of the SCM. To stack more layers, just add additional lines and bit lines, and the cells in between.
Even so, Kioxia is not optimistic about the prospects for 3D XPoint. The first is that the increase in the number of layers will bring greater complexity relative to the cost per bit of the number of layers, the loss of a portion of the control circuit will be a part of the area, and the impact of capacity loss will be greater.
By contrast, 3D NAND technology is much more mature, with a large number of products already on the market, and no one denies that layer stacking is an effective method because of its near-zero loss of area and very low loss of production.
During the manufacturing process, certain etching and filling steps for 3D NAND can cover many layers at a time. In contrast, 3D stacked SCM technology has not yet fully expanded beyond the market for single-tier devices.
Kioxia data shows that while its BiCS flash reduces to awful value sits at the cost per bit as it passes through 10 tiers, the 3D stack SCM can only reduce the cost of 4-5 to 60% of the cost per bit (and then soar surging thereafter) compared to a single-tier scenario.
The reason is that the latter has failed to benefit from decades of improved complex processes, resulting in increased costs per layer, loss of area, and decline in production. It’s a tough process to build 3D stack memory. For each extra step, the yield is even lower.
As shown in the above formula: where n is the number of layers, Cf is the cost of the common layer, Cv is the cost for each additional layer, A is the loss of area caused by adding a layer, and Y is the loss of output for a single layer.
In view of this, Kioxia noted at the meeting that in the case of 3D SCM, the cost per bit of about 12 floors is still equivalent. However, if the number of layers increases to NAND flash as much (in the case of 64-tier SCmOs), the cost per bit per tier increases to 50 times.
Even with strong push for support for 3D stacked SMs, stacking prediction costs above 4 layers today are already too high, without taking into account the potential for future technologies.
In summary, SCM does offer a large data pool in the memory world at a much lower cost per gigabyte than DRAM. But in the long run, flash memory will continue to dominate the industry for a long time to come.