Lee Jae-yong, Samsung’s de facto leader of electronics, today discussed Samsung’s strategic plan to use the world’s first 3nm process to make chips, South Korean media reported. Lee visited Samsung Electronics’ semiconductor research and development center in Hwaseong today, the report said. It was also Lee’s first official trip in 2020, during which he listened to Samsung Electronics’ 3nm process technology report and discussed a new generation semiconductor strategy with the head of the semiconductor division.
According to Samsung Electronics, Lee discussed Samsung’s plans to use the latest 3Nm All Gate (GAA) process technology under development to make cutting-edge chips. GAA is considered an upgrade to current FinFET technology that ensures that chipmakers further reduce the size of the chip.
Last April, Samsung Electronics completed the development of a 5nm FinFET process based on extreme ultraviolet technology (EUV). Today, the company is working on the next generation of nanotechnology technology, known as 3nm GAA. Samsung Electronics said that compared with the 5nm manufacturing process, the logic area efficiency of the 3nm GAA technology was increased by more than 35%, power consumption was reduced by 50%, and performance was improved by about 30%.
In response to Mr Lee’s visit to the Semiconductor Research and Development Center, a Samsung spokesman said: “Lee’s visit to the Semiconductor Research and Development Center today underlines Once Again Samsung’s commitment to growing into a top manufacturer in the “non-memory chip” market. “Samsung is currently the world’s largest memory chip maker.
Last year, Samsung announced an investment plan of 133 trillion won ($111.85 billion) to become the world’s largest maker of “system-grade chips” (SoCs) by 2030.