AMD introduced the 7nm Zen2 architecture this year, and has been fully upgraded in desktop and server versions, in addition to aPU and notebook versions. The next generation is the Zen3 architecture, which uses the 7nm EUV process, and the architecture design is now complete. What does the Zen3 architecture change from the current Zen2 architecture?
There is no official and definitive statement that the Zen3 architecture’s IPC performance will be increased by 8%, the core frequency will increase by about 200MHz, even if no more than 5GHz is infinitely close.
The Zen 2 processor has achieved the design of up to 16-core 32 threads on the desktop, the core number of the Zen3 processor is not expected to change, and the cache architecture will be the focus of improvement, after AMD officials said that unlike Zen 2 each set of CCX shares 16MB three-slow, Zen 3 provides 32MB of shared triple-slow for the whole core.
However, the latest leak said that AMD not only changed the structure of the L3 cache, but will further increase the capacity of the L3 cache to 48MB or even 64MB level, 50-100% more than the current Zen2.
Increasing the L3 cache can help solve the latency problem of AMD’s CCX architecture design, so that more data can be stored in the L3 cache, reducing calls to DRAM memory, after all, the natural latency on the separated IO core is higher than the native core, AMD can only minimize the latency in this way.
Of course, AMD’s ability to increase the L3 cache by half or half is also related to the new process, as the 7nm EUV process further increases transistor density on the existing 7nm, which lays the foundation for the L3 cache increase.
According to TMSC, the 7nm-EUV process improves performance by 10% compared to the 7nm process, 15% more energy efficiency, and a 20% increase in transistor density, a level of improvement that is not the level of a new generation of processes, or an optimized version of the improvement.