EU-led development of high-performance processors: ARM/RISC-V heterogeneous design, TSMC 6nm

Self-research processors seem to be entering an “arms race” linked to the geocamp. The European Union-led EPI initiative has unveiled a clearer roadmap,media reported. The project started as early as the third quarter of 2017, and the first chip was released late last year after several new members and draft technology were revised.

EU-led development of high-performance processors: ARM/RISC-V heterogeneous design, TSMC 6nm

According to the information published earlier, the chip will be used in the European Union developed supercomputer, using heterogeneous design, CPU part of the ARM system, the reference scheme is the “Zeus” iteration in the core of the Neoverese server, matching DDR5 memory, PCIe 5.0 interface and so on.

AI computing units (vector/volume core) are based on the RISC-V system and support FP32, FP64, INT8, bfloat16, etc., matching HBM memory chips.

It is worth mentioning that the chip was built by TSMC’s 6nm EUV process and is expected to be completed and delivered in volume by 2020.