Working with SiFive: GF completes HBM2E chip design in the first half of 2020

GlobalFoundries and SiFo announced Tuesday that they will jointly develop HBM2E memory based on the 12LP / 12LP plus FinFET process. The packaged IP enables SoC designers to quickly integrate HBM2E into chip designs that require a lot of bandwidth. Specifically, the HBM2E implementations of the two companies include a 2.5D package (middle layer) designed by Grofand and an HBM2E interface layer developed by SiFive.


(via AnandTech)

In addition to HBM2E technology, SiFive also allows the company’s RISC-V portfolio to be licensed, as well as Grofond’s 12/12LP plus DesignShare IP ecosystem, enabling SoC developers to build RISC-based based The device of V.

The companies noted that the implementation of the 12LP Plus manufacturing process and HBM2E will be primarily used for advanced AI training and inference applications, and that it is hoped that suppliers will optimize TOPS performance.

In addition, for Grofond, it requires a special process and may not be ready for TSMC (TSMC) and Samsung Foundry’s leading processes due to cost or other reasons.

As for the SiFive collaboration itself, it’s a bit tricky, after all, RISC-V itself is unlikely to be used for the core logic of the deep learning accelerator. But at the least, it is a reliable architecture that can be used to control the embedded CPU cores required to control the traffic in it.

It is reported that SiFive’s HBM2E interface, as well as custom IP for Grofont 12LP / 12LP plus technology, is under development at plant GF 8 in Malta, New York. The two companies expect to be able to complete their work in the first half of 2020, when IP authorization will be opened.

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