At last year’s CES 2019 show, Intel officially announced Foveros 3D stereo package technology, the first product codename, Lakefield. The biggest feature of the process is that it changes the practice of using the same process and placing different IP modules on the same 2D plane, to a 3D stereoscopic stack, and that different IP modules have the flexibility to choose the process that best suits them.
The benefit is that, supported by new packaging technologies, Lakefield can be classified as a new chip category – not only can be loaded into different computing cores for hybrid computation, but other modules can be loaded on demand, and performance and energy efficiency can be optimized within a very small package size.
Today, Intel officially unearthed Lakefield’s chip body and introduced the internal architecture. Really small enough to use the fingertips to gently pinch, need to use a magnifying glass to see.
Thanks to the addition of Foveros 3D stacking technology, The Lakefield chip is different from all of Intel’s past products – with a hybrid CPU design, a large core combined with four small cores.
Large cores use performance-prone microstructures, such as the 10nm Sunny Cove, while small cores use low-power microarchitectures, such as the next generation of Tremont.
Tremont instruction set architecture, micro architecture, security, power management, etc. have been improved in addition to the design requirements, in addition to the CPU, in addition to multiple functional modules, including the latest display chip and I/O functions.
With so many CPU cores and functional modules combined through Foveros 3D, the overall speed and energy consumption are exceeding expectations, which is unthinkable for traditional chips.
These features of the Lakefield platform mean that there are many advantages.
The first is small, small enough to be as small as a nail cap of 12mm x 12mm, and its motherboard is the size of a finger. Then there is the combination flexibility, Foveros 3D-based chips can be combined with different processes, different architectures, different functions of the module, for a seamless combination. Finally, the mode of hybrid computing, usually using a more energy-efficient core, maximize battery life, when needed to use a high-performance core, performance and energy saving can be done at the same time.
The combination of small, flexible, and hybrid computing in small, functional modules combines to open up revolutionary space for product design.
Prior to Foveros 3D, CPU chips were expanded in 2D, which meant that the increase in functional modules increased the area of the chip, meaning that it would sacrifice some performance and consume more power. And, at a time when transistors are increasingly dense, this form has almost reached its limit.
The magic of Foveros 3D is that it stacks logical chip modules layer by layer like a house, and when it can be 2D-turned-3D, performance is not lost and power consumption does not increase significantly.
This is a great advantage for Soc chips, because soc functions are complex, integrated modules are also many, after the use of Foveros 3D, different IP modules can be organically combined, not only the flexibility of chip design greatly improved, chip area, power consumption will be excellent performance, Ideal for the needs of new era mobile devices.
Lakefield is expected to be used in Microsoft’s Surface Duo dual-screen book, ThinkPad X1 Fold, and Samsung Galaxy Book S notebooks.