Intel’s “Fake 7nm” TSMC: N7 Process Node Naming Follows Convention Non-Physical Scales

Qualcomm’s SnapDragonX60 baseband based on Samsung’s 5nm process has been released, and TSMC will also be based on 5nm (N5) for Apple’s contract A14 and Huawei’s contracted Kirin 1020 chips in the second half of the year. Obviously, that doesn’t seem to be good for Intel, which is still grinding 14nm and struggling with 10nm supply capacity. However, Intel wrote back in 2017 to attack the industry’s confusion over the naming of process nodes.

Infographic (from: AMD)

Mark Bohr, then director of process architecture and integration, called on fabs to establish uniform rules to name advanced processes, such as transistor density. And by this standard, Intel’s 10nm is even better than the 7nm of the competition.

Since then, the anecdotal Tsing I faction shouted out Samsung, TSMC is “fake 7nm” slogan.

In response, TSMC’s head of marketing, Godfrey Cheng, responded at the AMD webinar event that, starting at 0.35 microns (350nm), the so-called process numbers no longer really represent the physical scale. He explains that 7nm/N7 is just a standard industry term, followed by N5 and so on.

He also believes that “a new descriptive language for process nodes needs to be sought.” “

As recommended by Intel, the logical transistor density (MTr/mm2, the number of million transistors per square millimeter) is used as an indicator to define the process node, taking into account the scanning trigger and NAND2 density, while reporting the size of the SRAM unit.