CPU Bull: Intel Retool Processor Development Process Design Speed SIUp

At the beginning of last year, Intel became the interim CEO of CFO, Schipper, as Intel’s official CEO, taking charge of the 51-year-old semiconductor giant. Mr. Srebo, a rare non-technical origin in Intel’s CEOs, has made a difference to a company that excels in technology? A few days ago, the U.S. media also interviewed Srebo, this time focused on how the 51-year-old semiconductor giant re-engineered. Srebo mentioned a number of reforms and key products intelly in recent years, such as 10nm capacity increases, small-chip-designed Lakefield processors, and more.

One of these involves Jim Keller, a well-known CPU architect who is now senior vice president and general manager of silicon engineering at Intel TSCG, whose main task is to continue to seek promotion under the guidance of Moore’s Law.

When Jim Keller arrived at Intel, he changed the CPU development process, where architects had little direct communication with process engineers and were accustomed to having large teams for each CPU project, not flexible enough.

Now Keller is pushing Intel to set up a number of small teams, and some new teams are focusing on developing standard integrated circuit modules that can be reused on different chips, so they can work independently without waiting for others to cooperate.

Jim Keller says these process improvements have reduced intel’s time to develop and test chip changes from weeks to days, and now create a new full chip design three times faster.

CPU Bull: Intel Retool Processor Development Process Design Speed SIUp

In short, from Jim Keller’s statement, Intel reform CPU development testing process, efficiency is greatly improved, the development of new CPU time can only be used by 1/3.

But for downstream users, These changes seem to have not come to light, as most people still see a 14nm processor, a 10nm desktop processor without a sound, and will inevitably be unhappy with Intel’s slow motion.

CPU Bull: Intel Retool Processor Development Process Design Speed SIUp