The 2015 AMD Fury X graphics card, codenamed Fiji, was released, representing the first time HBM memory has entered the public eye. The traditional 2D memory is directed into the stereospace, and by stacking, a single DIE can achieve 8GB capacity and a bit width of up to 1024bit. In contrast, the traditional memory sheet Die has only 1GB capacity and a bit width of only 32bit.
Therefore, HBM memory can easily achieve 32GB capacity, 4096bit bandwidth, without the need for too high frequency to achieve the traditional GDDR5 memory can not reach the horror bandwidth.
In 2017, with the advent of the Zen-framed Ryzen processor, AMD also brought us to the mcM (Multichip Module) technology. The modular-designed Ryzen processor has eight cores in a single CCD, which can be packaged into 4 cores, and the 32-core Tearer 2990WX has 4 CCDs.
The advent of MCM technology makes multi-core expansion simpler and more efficient, while avoiding the problem of yield from the big core, so it is far better than the competition in cost.
The 2019 Zen 2 architecture has upgraded MCM technology to Chiplet once again. By separating CPU Die from I/O Die, CPU Die can do less, expand more cores and become easier, while further reducing the manufacturing costs of multicore processors. According to AMD, in some cases, the Chiplet design can reduce processor manufacturing costs by more than half.
At amd financial analysis this morning, AMD CEO Su Zifeng showed you a packaging technology called X3D, which adds HBM’s 2.5D stacked package to the original Chiplet technology. Although AMD doesn’t say, the intent is clear, and the future of high-performance processors is likely to introduce HBM memory, increasing memory bandwidth by more than 10 times.
If all goes well, we’ll see this design on the Zen 4 architecture, and the performance of the next generation of AMD processors is pretty promising!