In recent days, IBM has revealed many technical details of its next-generation host, the IBM z15, which once again highlights the strength of the Blue Giant, especially with its staggering cache capacity and density. The IBM z15 integrates 12.2 billion transistors, 2.5 billion more than the previous z14, with 12 physical cores per chip, with a total area of 696 square millimeters, the same as the previous generation.
IBM z15, z14 core specification comparison
The cache is divided into four levels, one or two of which are integrated within the core, three or four levels are outside the core, and the capacity is greatly enhanced: 128KB per core level instruction cache, 128KB of primary data cache, total capacity of 3MB; Double from the previous generation.
The third-level cache doubled from 128MB to 256MB, while the four-level cache increased almost by half from 672MB to 960MB.
This adds up to a staggering 1315MB of four levels of cache capacity per processor.
In terms of frequency, the first-and-two-stage cache runs at 5.2GHz like the CPU core, while the third-level cache is a half-speed 2.6GHz.
IBM z15 four-level cache
Even more striking is that the IBM z15 manufacturing process is still the 14nm FinFET SOI developed jointly by IBM and GlobalFoundries. The cache has increased so much that the total area remains the same, when it’s a treasure knife.
In addition, the two- or four-stage caches of z15 are high-density eDRAM storage units with an area of 0.0174 square microns per unit, even higher than the SRAM density under TSMC’s 5nm process, which is 0.021 square microns per unit.
Of course, this comparison is not entirely accurate, because SRAM is usually six transistors per unit, eDRAM is one, but also enough to see the 14nm process of the fire pure green.
David Schor, an analyst at WikiChip, also said the IBM/GF 14nm has proven to be excellent.
SRAM Integrated Density Comparison of Leading Process